A 56-Gb/s PAM4 Receiver With Low-Overhead Techniques for Threshold and Edge-Based DFE FIR- and IIR-Tap Adaptation in 65-nm CMOS (2025)

IEEE Journal of Solid-State Circuits, volume54, issue3, pages672-684

Ashkan Roshan Zamir 1

,

Takayuki Iwai 2

,

Yang-Hang Fan 3

,

Ankur Kumar 3

,

Hae-Woong Yang 3

,

Lee Sledjeski 4

,

JOHN HAMILTON 4

,

Soumya Chandramouli 4

,

Arlo Aude 4

,

Samuel Palermo 3

Hide authors affiliations Show authors affiliations: 4 affiliations

1

Texas Instruments Incorporated, Santa Clara, CA, USA |

2

Toshiba Memory Corporation, Kawasaki, Japan |

3

|

4

Texas Instruments Incorporated, Duluth, GA, USA |

Publication type:Journal Article

Publication date:2019-03-01

A 56-Gb/s PAM4 Receiver With Low-Overhead Techniques for Threshold and Edge-Based DFE FIR- and IIR-Tap Adaptation in 65-nm CMOS (1)

Institute of Electrical and Electronics Engineers (IEEE)

Journal: IEEE Journal of Solid-State Circuits

scimago Q1

wos Q1

SJR:2.876

CiteScore:11.0

Impact factor:4.6

ISSN:00189200, 1558173X

Electrical and Electronic Engineering

Abstract

This paper presents a four-level pulse amplitude modulation (PAM4) quarter-rate receiver that efficiently compensates for moderate channel loss in a robust manner through background adaptation of the receiver thresholds and equalization taps. The front-end utilizes an input single-stage continuous-time linear equalizer (CTLE) to boost the main cursor and relax the pre-cursor cancellation requirement, requiring only a 2-tap pre-cursor feed-forward equalizer (FFE) on the transmitter side. A 2-tap decision feedback equalizer (DFE) follows that includes one finite impulse response (FIR) tap and one infinite impulse response (IIR) tap to cancel first post-cursor and long-tail inter-symbol interference (ISI), respectively. In addition to the per-slice main three data samplers, a single error sampler is utilized for background threshold control and an edge-based sampler performs both phase-locked loop (PLL)-based clock and data recovery (CDR) phase detection and generates information for background DFE tap adaptation. Fabricated in general purpose (GP) 65-nm CMOS, the 56-Gb/s receiver achieves 4.63 mW/Gb/s and compensates for up to 20.8-dB loss at a bit error rate (BER) <; 10-12 when operated with a 2-tap FFE transmitter.

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A 56-Gb/s PAM4 Receiver With Low-Overhead Techniques for Threshold and Edge-Based DFE FIR- and IIR-Tap Adaptation in 65-nm CMOS (2025)
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